Immersion resist process for 32-nm node logic devices
2008
Key issues of resist process design for 32nm node logic device were discussed in this paper. One of them is reflectivity
control in higher 1.3NA regime. The spec for the reflectivity control is more and more severe as technology node
advances. The target of reflectivity control over existent substrate thickness variation is 0.4%, which was estimated from
our dose budget analysis. Then, single BARC process or stacked mask process (SMAP) was selected to each of the
critical layers according to the substrate transparency. Another key issue in terms of material process was described in
this paper, that is spin-on-carbon (SOC) pattern deformation during substrate etch process. New SOC material without
any deformation during etch process was successfully developed for 32nm node stacked mask process (SMAP). 1.3NA
immersion lithography and pattern transfer performance using single BARC
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