Modeling and sizing of non-linear CMOS analog circuits used in mixed signal systems

In this paper, modeling of performance parameters and time efficient yet accurate sizing methodology of CMOS analog non-linear circuits have been proposed. The proposed modeling methodology generates empirical models of the non-linear circuit performance parameters in monomial or posynomial form, which is geometric programming (GP) compatible, as a function of the final design variables of the circuit (i.e. the width and length of the transistors). The proposed non-linear circuit sizing methodology, referred to as iterative geometric programming utilizes a correction factor for each of the GP compatible performance parameter models. These correction factors are updated using SPICE simulation after every iteration of the GP optimization. The proposed methodology takes advantage of GP optimization and at the same time it uses SPICE simulation to improve the design point by rectifying inaccuracies that may exists in the GP compatible performance models. Both the proposed methodologies have been validated in a 0.18 μm CMOS technology. The dynamic comparator and the bootstrap switch which are commonly used non-linear circuits in analog-mixed signal systems, have been used as the example circuits. It has been observed that the proposed sizing algorithm converges rapidly and give final design point with SPICE level accuracy higher than 99 %. The efficiency and the accuracy of the proposed algorithm has been numerically compared w.r.t. the sizing algorithm using evolutionary algorithm. It has been observed that the proposed algorithm gives much better results. Moreover, the proposed algorithm is hundreds times faster than that of the evolutionary algorithm.