A 6-Bit, 29.56 fJ/Conv-Step, Voltage Scalable Flash-SAR Hybrid ADC in 28 nm CMOS

This paper presents the design of a 6-bit scalable hybrid flash SAR (successive approximation register) analog-to-digital converter (ADC). The ADC has a scalable architecture because of the usage of an inverter based comparator. The conversion time is reduced by adopting a 3-bit/cycle approach. A segmented split-capacitor charge redistribution digital-to-analog converter (CDAC) is used to reduce the DAC settling time and the design area. The ADC is implemented in a 28 nm CMOS technology with the scalable V DD from 0.5 V to 1 V. The ADC operates from 10 MHz to 1.1 GHz for a V DD of 0.5 V to 1 V respectively. The design shows 47.7 fJ/conv-step and 29.56 fJ/conv-step for V DD of 0.9 V and 0.6 V respectively.