Hot-carrier reliability study and simulation methodology development for 65nm technology

In this work, we report degradation study in 65nm technology NMOS I/O transistors (Tox=55 A) for different channel widths. Devices were stressed at maximum substrate current condition in order to stimulate HCI degradation. These measurements were validated using analytical equations and reliability models extracted to be compatible with Eldo simulation tool using User Defined Reliability Model (UDRM) approach.