SiGe and Ge on Insulator Wafers

Since 90nm technology Germanium (Ge) element has become increasingly popular in the CMOS processing for enhancing transistor performance, especially enhancing hole mobility for P-type transistors. The main driver has been the embedded SiGe in the source/drain region and its extraordinary boost on PFET drive current [1]. More recently Ge has enabled band engineering with respect to Silicon for Vt tuning [2,3] in addition to channel engineering for mobility enhancement. Looking into the future the need for SiGe alloys or pure Ge is increasing, as it is contemplated as a seed for IIIV material growth [4], or even the replacement of Si by Ge in the channel to take advantage of the high electron and hole mobilities [5]. Today the manufacturing reality shows us that all Ge needs can be fulfilled by epitaxy during the processing of the devices [6]. In this paper we will introduce the Dual Channel substrate having a strained SiGe layer grown on top of a SOI substrate. Starting with this wafer and thru condensation process one can produce a uniform SiGe layer suitable for Fully Depleted applications.