Reliability of Wafer-Level Ultra-Thinning down to 3 µm using 20 nm-Node DRAMs

3D integration (3DI) with bumpless Wafer-on-Wafer (WOW) technology is expected to be one of the most promising methods for improving device performance. One of the key points of this technology is how to reduce the Si as thin as possible without degrading the device characteristics. In this work, ultra-thin DRAMs with 5 µm- and 3 µm-thick Si wafers have been developed for WOW applications. The influences of Cu contamination and backside defects on device reliability were evaluated using 3 µm-thiek Si wafer for the first time. The backside defects were compared with thinning methods using grinding and chemical mechanical polishing (CMP), respectively. It was found that the refresh time according to the normalized failure rate below 10 -6 was shortened due to Cu contamination after CMP process. The refresh time was improved by increasing the thickness of the backside defects layer using grinding. However, these defects may cause degradation of the standby currents when the Si thickness closes to depletion region at 3 µm in thickness. Thus, it is important how to design the diffusion length of defects carefully to prevent incoming defects to depletion layer, taking the standby currents and the retention characteristics into account.