Optimization and hardware implementation of image watermarking for low cost applications

In many resource/power constrained applications (e.g., in wireless-network nodes) there is a need for low cost hardware implementations of digital image watermarking techniques. However, to end up with such an implementation, a proper selection of a watermarking technique, based on performance and cost criteria, is not enough. For that reason, in this paper we introduce computation optimizations of the implemented algorithm to keep the integer portion of arithmetic operations at optimal size, and, hence, arithmetic units as small as possible. Additionally, the proposed architecture reutilizes those units in different computation steps, to further reduce implementation cost. The proposed design compares favorably with the already existing implementations, in terms of area, power and performance.