A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros

The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-μm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.