Thermal-aware network-on-chips: Single- and cross-layered approaches

Abstract In the era of the billion transistors on a chip that are capable of implementing thousands of processing cores, Network-on-Chips (NoCs) are the most viable and scalable solution to connect this massive number of cores. NoCs gradually support manycore processors technology, from conventional ICs with tens to hundreds of cores to 3D integrated ones with even more cores. On the other hand, many challenges arise over time that impede the growth of such enabling technology. The thermal problem is still a serious example of NoC design complications that can greatly limit NoC designs. This forces designers to model, design, and innovate new tools and techniques either offline or at runtime to measure, manage, and solve thermal problems. As a sequel, various techniques have been introduced, covering all layers from the top-most networking application layer to the bottom most-physical layer. In this survey paper, the authors put their hands on various designs and modeling techniques for thermal-aware NoC management. Most importantly, key ideas and research directions are classified, pointed out, and demonstrated with a reasonable amount of details that enables interested researchers to come up and grasp all research directions for thermal-aware NoC technologies.