Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM

This paper presents a dual-loop 2-step ZQ calibration scheme with 20nm DRAM process to support dedicated supply voltage (VDD, VDDQ). The proposed calibration scheme maintains a target value of on-die termination (ODT) in DQ/CA regardless of the supply-voltage variations which are caused by dynamic voltage frequency switching (DVFS) and alleviates the calibration time which is increased by insertion of additional CA calibration. The offset of a comparator is averaged out by fraction-referred input switching-then-averaging scheme (FISA). And code-referred periodic ZQ update (CPZU) scheme can track the VT variation while minimizing the interference.