A 125 μ m × 245 μ m Mainly Digital UHF EPC Gen2 Compatible RFID Tag in 55 nm CMOS Process

This paper presents a compact and largely digital UHF EPC Gen2-compatible RFID implemented using digital IP blocks that are easily portable. This is the first demonstration of a digital Gen2-compatible RFID tag chip with an area of $125{\mu }\text{m} \times 245{\mu }\text{m}$ and −2 dBm sensitivity operating in the 860–960MHz band. It is enabled by a) largely standard cell-based digital implementation using dual-phase RF-only logic approach, b) near-threshold voltage operation, and c) elimination of area intensive, complex, and less scalable rectifiers, storage capacitors, and power management units used in conventional RFID tags. In this demonstration, all but six cells were directly used from the standard cell library provided by the foundry. This makes it suitable for cost-sensitive applications, and as embedded RFIDs for tagging counterfeit Integrated Circuits (ICs).