Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling

The paper proposes a novel practical replacement of conventional high-speed clock-gates for wide voltage scaling. The proposed clock-gate enhances the energy-delay-product by 43% and improves the low-voltage operation by 50 mV reducing the sampling window by 31% as compared with a conventional high-speed pulse-base clock-gate. The comparison also indicates 50% speed improvement resulting in up to 60% EDP reduction as compared with conventional low-power clock-gates. A test chip was fabricated using a 14 nm CMOS FinFET process with five representative process corners, SS, TT, FF, SF and FS, and measured under three temperature conditions, −25°C, 25°C and 100°C, for production-level silicon verification.