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Dae-Seong Lee
Dae-Seong Lee
Samsung
Electronic engineering
Process corners
Logic gate
Chip
Voltage
2
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Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling
2018
ISCAS | International Symposium on Circuits and Systems
Min Su Kim
Ah-Reum Kim
Yong-geol Kim
Chung-Hee Kim
Dong-Yeop Kim
Jong-Woo Kim
Dae-Seong Lee
Hyun Cheol Lee
Jungyul Pyo
Youngmin Shin
Jae Cheol Son
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Single-ended D flip-flop with implicit scan mux for high performance mobile AP
2016
SoCC | System-on-Chip Conference
Min Su Kim
Chung-Hee Kim
Yong-geol Kim
Ah-Reum Kim
Ji-Kyum Kim
Juhyun Kang
Dae-Seong Lee
Changjun Choi
Ilsuk Suh
Jungyul Pyo
Youngmin Shin
Jae Cheol Son
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