Applications and Reliability Study of InFO_UHD (Ultra-High-Density) Technology

Inter-chip interconnect pitch miniaturization has become an essential part to enhance die-die communication bandwidth (BW) performance in advanced packaging technology. Among different inter-chip interconnect approaches reported [1]-[9], a fan-out technology with RDL could be the simplest integration approach. RDL scaling capability has been severe challenge. InFO_UHD technology [1] has been proposed to provide submicron pitch inter-chip RDL. InFO_UHD applications to high performance computing is discussed in the first part of this paper. A case study using InFO_UHD for two-chip integration in networking was examined, as ~4X total bandwidth can be reached under InFO_UHD L/S (RDL Line-width/Line spacing) 0.8/0.8μm versus L/S 2/2μm case. Additionally, benefits of fine line applications on chiplet integration would also be addressed. The second part of this paper shows the electrical and reliability evaluation results for networking application, where InFO_UHD test vehicle was designed with inter-chip RDL line-width 0.8μm in interconnect levels. This test vehicle mimics real products of two-die structure with organic substrate. Package level electrical properties demonstrate nearly 100% yields, and package level reliability testing results, such as Multiple-Reflow (MR), Thermal Cyclic Test (TC), Highly Accelerated Stress Test (HAST; both biased and un-biased), High Temperature Storage Test (HTS), will be disclosed. Interconnect reliability for Electro-migration (EM) and Stress-migration (SM) will be presented as well.