A 5-/spl mu/m/sup 2/ full-CMOS cell for high-speed SRAMs utilizing a optical-proximity-effect correction (OPC) technology

A 5.01-/spl mu/m/sup 2/ full-CMOS SRAM cell using a 0.28-/spl mu/m design rule has been developed and the cell operation at as low as 0.6 V was confirmed. This cell has been designed not only to be small but also to be widened bitline pitch for reduction of bitline delay. To realize this cell, optical-proximity-effect correction (OPC) and some technologies for cell-size reduction have been adopted. In addition, glue layer wiring (GLAW) for the local interconnection has been used in order to simplify the process.