Cu barrier properties of very thin Ta and TaN films

As a result of the continuous miniaturization of integrated circuits, width and depth of Cu interconnects are reduced for every new technology node, implying that also the Ta or TaN Cu diffusion barrier and Cu seed layer must be thinned in order to avoid top feature pinch-off during Cu electroplating [1]. On the other hand, a reduction of Ta or TaN film thickness may also be desirable from a cost perspective, e.g. in ICs with less aggressive scaling. Cabral et al. showed that a 1 nm TaN film prevented Cu diffusion upon annealing at temperatures below 650 °C [2]. However, no electric fields were applied in this study, and TaN was deposited on Si.