Development of core-less substrate for multi wiring layers
2002
A chip size package (CSP) and fine pitch ball grid array (FBGA) are increasing by becoming the focal point of attention in semiconductor field. A reel-to-reel consecutive manufacturing process has been developed by the authors for a tape-based substrate consisting of multi conductive wiring layers (minimum four layers) with ball grid array connections. This substrate, compared to those presently in use, is (a) thin (150/spl sim/200um for four layers) and low weight; (b) applicable to many pin counts; (c) makes possible fine conductive wiring and insulating layers with high accuracy in layer thickness and (d) facilitates the control of characteristic impedance. Interlayer connection technology is key to multi-conductive wiring layer structures, which may have effect primarily on substrate reliability. In the present study, a copper deposited plating process was used in conjunction with UV-laser drilling so as to produce very small via-holes in diameter 40-50um as interlayer connections. The reliability of interconnections was confirmed for via-holes with diameter 40-50um under the condition of 1000cycle thermal shocks of -65C/+150C a gaseous phase. Filled via-hole formation without interior voids was found to take place in the plating process. Minute stacked via-hole formation was noted to provide a substrate with high density pin counts. The substrate structure was designed with consideration electromagnetic transmission characteristics by computer simulation. The present substrate meets recent requirements for GHz order signal transmission.
Keywords:
- Correction
- Source
- Cite
- Save
- Machine Reading By IdeaReader
5
References
1
Citations
NaN
KQI