Cylindrical Ru-SrTiO/sub 3/-Ru capacitor technology for 0.11 /spl mu/m generation DRAMs

We have developed a cylindrical Ru/ST/Ru capacitor for gigabit-scale DRAMs. Using cylindrical CVD-Ru as a storage node (SN), a new 2-step CVD-ST was employed to improve ST step coverage, surface morphology and to control composition at the Ru/ST interface. A SiO/sub 2/ equivalent thickness (t/sub eq/) of 0.6 nm and cell capacitance of 18 fF/cell with leakage current of 0.1 fA/cell at /spl plusmn/0.7 V applied voltage has been achieved on a 256K cylindrical Ru/ST/Ru capacitor array.