Cleans for Al vias in a 0.175 /spl mu/m dual damascene process

The effect of cleaning processes on via resistance and via continuity has been studied for 0.175 /spl mu/m Al dual damascene structures used for 1 Gbit DRAMs. Three types of vias have been investigated; high aspect ratio (4:1) Al vias landing on either W or Al damascene interconnects, and relatively low aspect ratio (1.3:1) Al vias landing on Al damascene interconnects. The via resistance depends on both the type of contact and the type of clean. Low via resistance is more difficult to achieve when landing on Al compared to landing on W, due to the low volatility of Al fluorides and due to the high thermal stability of Al oxides.