Hybrid silicon nanocrystals/SiN charge trapping layer with high-k dielectrics for FN and CHE programming

Silicon nanocrystal (Si-nc) trapping layers offer several advantages on standard poly-Si floating gates, as improved data retention after endurance in particular at high temperatures [1][2], robustness toward oxide defects, two-bits per cell storage and full compatibility toward CMOS process. It has also been shown that coupling the Si-nc concept with high-k control dielectrics, by improving the gate coupling ratio, enables Fowler-Nordheim (FN) program/erase [3]. However, one of the key limitations of Si-nc memories is the limited memory window which is not suitable for multi-level memory applications. The use of two stacked Si-ncs layers to increase the number of trapping sites has been previously discussed in the literature with a SiO 2 control oxide [4]. In this work, we present memory devices with double stacked Si-nc layers and high-k (HfAlO-based) control dielectrics. We also propose to cover the 2 nd Si-nc layer with a thin nitride layer (leading to an hybrid Si-nc / SiN memory structure [3][5]) in order to boost further the memory characteristics. We will show that these devices offer improved memory programming window both in FN regime [6] and in channel hot electron injection (CHE), which makes them compatible with NAND and NOR applications. Finally, a model involving valence band electrons from the top Si-ncs layer is proposed to explain the electrical results.