Next generation of transparent processors for broadband satellite access networks

This paper presents possible payload / processor architectures, responding to the requirements of the next generation of broadband access networks via satellite, targeting throughputs higher than 50 Gbps. First the transparent satellite access system scenario is described and the main payload and processor requirements are identified. Then the main part of the paper trades off different payload and processor architectures taking into account major constraints such as flexibility, scalability, complexity, mass and power consumption. It identifies respectively “beam port processor architectures” where no beam forming is performed inside the processor and “feed port processor architectures”, which involve digital beam forming. The different payload and antenna front-ends likely to accommodate these processors, such as single feed per beam and array fed-reflectors, are also discussed. Finally system capacity analysis is performed to demonstrate the targeted system performances.