Design-aware Partitioning-based 3D IC Design Flow with 2D Commercial Tools

Three-dimensional (3D) ICs can continue to improve power, performance, area and cost beyond traditional Moore’s law scaling limitations by leveraging the third-dimension and short vertical interconnects. Several recent studies present methodologies to implement 3D ICs, but most of these studies implement each tier separately after partitioning a design into multiple tiers, resulting in inaccurate buffer insertion, which becomes more severe in advanced technology nodes. In this paper, we present a new methodology called ‘Cascade2D flow’ which utilizes design and micro-architecture insight for tierpartitioning and implements 3D ICs using 2D commercial tools. By modeling vertical interconnects with sets of anchor cells and dummy wires, Cascade2D flow places, routes and optimizes multiple tiers simultaneously in the 2D version of a 3D IC called ‘cascade2D design’, which enables accurate buffer insertion. Two flavors of 3D ICs – monolithic 3D (M3D) and face-toface- bonded (F2F-bonded) 3D ICs – of a commercial, in-order, 32-bit application processor at foundry 28 nm, 14/16nm and predictive 7nm technology nodes are implemented using this new methodology. We investigate the power, performance and area improvements of 3D ICs over the 2D counterparts to examine the efficacy of the methodology. Our new methodology outperforms the state-of-the-art 3D IC design flows in the both flavors of 3D ICs with up to 4× better power savings. In the best case, 3D ICs from Cascade2D flow show 25% better performance at iso-power and 20% lower power at iso-performance.