Analysis of a passive UHF RFID tag analog front-end consuming 1 uA compliant with the EPCglobal Class1 Gen2 standard

This paper presents the design of an analog front-end of a passive UHF RFID tag compliant with the EPCglobal Class 1 Generation 2 standard. To enable long-range operation of passive tags, the power consumption must be minimized. In this work, the front-end consumes 1uA at the minimum supply voltage of 1.2V and features a RF to DC rectification efficiency of 36.9%. As technology, a TowerJazz Standard Logic 0.18um process with Schottky diodes is used. Several energy-saving techniques are employed and explicated. A novel zero-to-absolute-temperature (ZTAT) structure is introduced, enabling the efficient generation of a stable clock frequency with ±1.8 % dynamic change. The backward signal power is examined and equals −75 dBm at a distance of 17m. The theoretical sensitivity of the analog front-end itself is −24 dBm.