wilth H'ighly Enhanced Strailn andFull-Porous Low-kInterconnects for45-nmCMOS Technology

technology. Toachieve aggressively-scaled active, poly, conWe present anaggressively-scaled high-performance and tact, andmetal pitches andthustocreate 2xpattern density, low-power bulk CMOSplatform technology aiming atlarge-scale high-NA 193-nm immersion lithography wasusedtoexpose the (multi-core) high-end usewith45-nmground rule. Byutilizing a critical layers. TheFEOLprocess flow inwhich MSTisthebooster high-epsilon offset spacer andFETspecific multiple-stressors