Is there an impact of threading dislocations on the characteristics of devices fabricated in strained-Ge substrates?

The electrical impact of threading dislocations in strained-germanium (s-Ge) grown on a strain-relaxed Si0.2Ge0.8 buffer is investigated by means of the current-voltage (I-V) and capacitance-voltage (C-V) characteristics of p+n and n+p junctions fabricated in these layers. For comparison, reference devices with a two to three orders of magnitude lower threading dislocation density (TDD) have also been studied. While the leakage current of the s-Ge diodes is about two decades higher, indicating an overall correlation with TDD, the impact of a post-growth anneal cannot be explained by a removal of TDs. Instead, it is believed that the heat-treatment-induced improvement of the reverse current is associated with the removal of point defect clusters from the SiGe buffer layers. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)