Packaging of high speed 100 Gbps silicon photonic photoreceiver module using 50 µm pitch microbump flip-chip and chip-on-board approach

Growing demand for bandwidth in datacom optical links and for high performance computers (HPC) recently led to the development of new optoelectronic modules based on silicon photonic integrated circuits (PIC) [1]. One of the intrinsic capabilities of this technology is the scalability in terms of aggregated data rate, due to the possibility of combining space division multiplexing (SDM), wavelength division multiplexing (WDM), and the use of advanced modulation formats such as PAM4 or QPSK [2]. In this work, we describe compact multichannel PIC-based photoreceiver modules designed for 100 Gbps aggregated bandwidth transmission. Both SDM and WDM configurations were processed and tested. These modules require specific packaging design for the high data rate electrical connection between the PIC and the electronics, and for the multichannel fiber optic connection. We brought the design of the module to the full package, including stacking of the electronic chip onto the PIC, motherboard implementation, and fiber pigtailing.