Study on Dynamic Body Bias Controls of RF CMOS Cascode Power Amplifier

This letter presents a highly linear cascode CMOS power amplifier (PA) that uses dynamic body linearizers based on envelope signal injection to the bodies of the common source and common gate power transistors. The linearizers allow the PA to have optimum AM–AM and AM–PM, which reduces the nonlinear distortions significantly. The two-stage PA is fabricated using a 0.18- $\mu \text{m}$ CMOS process with a printed circuit board output transformer. At 1.85 GHz, it delivers 27.7-dBm output power with 41.3% power added efficiency under a −33-dBc ACLR $_{\textsf {E-UTRA}}$ and a 4.7% error vector magnitude using long term evolution (LTE) signal.