Improving the Burst Error Tolerance of Irregular LDPC by Optimizing the Parity-Check Matrix Column Arrangement for 50G-PON Upstream Transmission

We demonstrate a novel technique to improve the burst-error-correction performance of the irregular LDPC code used for 50G-PON upstream transmission by optimally rearranging the parity-check matrix columns. FPGA-based real-time measurements show over 0.2 dB gains.