Wave Pipelining YADDs – A Feasibility Study

In this paper we study circuit structures obtained from direct mapping to pass transistor logic (PTL) of Yet Another Decision Diagrams (YADDs). These structures have almost equal delays along all the paths which makes wave pipelining possible. We discuss the details of a complete design, clocking and layout. In 0.5 /spl mu/m CMOS technology, YADDs can be clocked at a fixed rate of 715 MHz for any function. Our experimental results suggest that 4 times increase of speed over standard cell design is on the average possible for the price of similar area increase.