Interface engineering for the TaN/Ta barrier film deposition process to control Ta-crystal growth

As a consequence of device shrinking the resistivity of the widely used TaN/Ta double barrier layer becomes an increasingly important parameter for device speed beyond the 32nm technology node. In this study we describe the optimization of the deposition of TaN/Ta stacks in such a way that tantalum nitride layer thickness is minimized and tantalum grows in the favorable conducting @a-phase. In the first part of the study we used in situ ARXPS to investigate the growth of different tantalum nitride layers on SiO"2 and SiOCH as a function of deposition time, nitrogen flow and deposition power. In the second part we analyzed the crystalline phase of a 20nm thick tantalum layer deposited on top of the same series of tantalum nitride layers characterized in the growth study. The main findings are the appearance of tantalum carbide and tantalum silicide as interface species for the deposition on SiOCH and only tantalum silicide for the deposition on SiO"2. We found that @a-tantalum grows preferably on tantalum carbide and nitrogen rich intermediate layers whereas silicide at the interface promotes the growth of @b-tantalum. To verify these findings we studied two additional modifications of the interface. A lower bias power for a deposition of tantalum nitride on SiO"2 was used to confirm the role of tantalum silicide and a thermal treatment of a thin tantalum layer on SiOCH was applied to confirm the role of tantalum carbide. Finally, the contact resistance in via chains on patterned wafers for four selected processes showed the same trends as the sheet resistance of the corresponding barrier films on blanket wafer experiments.