Advanced contact and junction technologies for improved parasitic resistance and short channel immunity in FinFETs beyond 22nm node

Advanced, fully depleted devices such as FinFET or Tri-Gate transistors are increasingly sought after to enable density and gate length (L g ) scaling in future technology nodes. As gate-pitch scaling continues, the fin pitch must also be reduced to maintain proper electrostatics control in short L g devices. However, in the absence of proper junction engineering, further scaling of L g below 10nm would compromise off-state leakage (I off ) due to degraded drain-induced barrier lowering (DIBL) and subthreshold slope (SS) as a result of poor short channel control. This may be mitigated by scaling the gate dielectric thickness to maintain good control of short-channel effects (SCE), but it leads to an exponentially increasing gate leakage current and power consumption. Increasing channel doping could be an alternative to improve SCE, but it decreases carrier mobility due to impurity scattering and gives rise to random dopant fluctuations (RDF) issue. Additionally, decreasing the fin pitch to preserve short channel integrity reduces the source/drain (S/D) contact area which leads to an increase in external parasitic resistance (R ext ) that has become a critical technology barrier to achieving ITRS's performance target in advanced nodes.