RF FET layout and modeling for design success in RFCMOS technologies

This paper presents challenges in creating high quality RF FET layouts and models in CMOS technologies spanning 0.25 /spl mu/m to 90 nm nodes. The focus is on developing a comprehensive methodology to provide robust, high performance parameterized RF FET layout cells and corresponding scalable RF models to enable RF designs that fully leverage the cost benefit potential of CMOS technology.