Novel Process Development for Bilayer Embedded SiGe Source/Drain Formation

We developed a new technique of bilayer embedded SiGe epitaxy for suppressing degradation of short channel characteristics in PFET. We found that the SiGe growth rate near the recess gate edge increased by applying a high DCS flow rate with a high-pressure condition. It enabled 1 conformal undoped SiGe layer growth for the recess shape. For the 2 SiGe layer, we used an appropriate B2H6 flow rate for good morphology. In addition, we developed a simultaneous condition switching technique for bilayer embedded SiGe. Introduction Various stress induced mobility-enhancing technologies have been developed. Embedded silicon germanium (SiGe) source/drain is one of them[1,2]. In-situ B-doped SiGe epitaxy is desirable because deep implantation into a SiGe source/drain region degrades device characteristics[3]. However, this type of epitaxy causes B to diffuses during the followed process and the short channel characteristics degrade[4], so we developed a new technique of bilayer SiGe epitaxy by using conformal SiGe growth and simultaneous condition switching. Experiment Conformal Undoped SiGe growth for the 1 layerFig. 1(a) is a schematic of the SiGe growth and (b) is the cross-sectional TEM of SiGe epitaxy with a facet condition after recess etching. It shows almost no growth on the recess gate edge. Inserting a undoped SiGe layer near the gate edge is effective for suppressing degradation in short channel characteristics, so we tried a new condition. Fig. 2 shows a cross section of (a) a high DCS flow rate and (b) high pressure with a high DCS flow rate SiGe condition. The growth rate ratio between the X and Y direction became closer in the latter condition, as shown in Fig. 3, indicating conformal SiGe growth for a recess shape. Facet B-doped SiGe growth for the 2 layerFor the 2 layer of in-situ B-doped SiGe, the appropriate B2H6 flow rate must be chosen for good morphology of SiGe, as shown in Fig. 4. Bilayer SiGe growthProcess condition switching is important for fine epitaxial growth in bilayer SiGe. Because the SiGe surface is supposed to be damaged by HCl more easily than Si, a hydrogen purge between the 1 and 2 layer is inadvisable. The reason is that the initial gas flow of the 2 SiGe layer with HCl followed by a hydrogen purge easily etches 1 SiGe surface. Consequently, the bilayer SiGe surface becomes bad morphology, as shown in Fig. 5(a). The new technique of simultaneous condition switching resulted in better morphology than that achieved with the previous sequence, as shown in Fig. 5(b). Fig. 6 shows PFET that uses this technique. No defects are evident in the SiGe region. Conclusion We developed conformal undoped SiGe growth and used the appropriate B2H6 flow rate for 2 facet SiGe growth. In addition, we achieved bilayer SiGe with good morphology and no defects using a new technique of simultaneous condition switching. Acknowledgement The authors would like to thank ASM Japan K.K. for their technical support. References [1] S. Tyagi, et al., IEDM Tech. Dig., pp. 1070(2005). [2] Q. Ouyang, et al., Symp. VLSI Tech. Dig., pp. 28(2005). [3] D. Zhang, et al., Symp. VLSI Tech. Dig., pp. 26(2005). [4] K. Ota, et al., submitted to VLSI symposium (2006).