Electrical testing of blind Through-Silicon Via (TSV) for 3D IC integration

In this study, a method to test blind TSVs in 3D IC integration for their electrical performance is investigated. Emphasis is placed on the development of a novel blind-TSV method by electrical testing on the top side of the TSV-wafer before backgrinding. Through leakage current testing, it is possible to determine whether there is short circuit between blind TSVs. Most conventional measurement methods can only be performed after wafer thinning to reveal the TSVs Cu and/or backside processing, which could lead to a higher manufacturing cost of 3D IC integration products if the electrical performances of the manufactured TSV don't meet the specification. Also, by providing analysis flow of high frequency simulation and measurement, we can define the thickness of the isolation layer (Silicon dioxide, SiO 2 ) of blind TSV into specification. Furthermore, the analysis flow can obtain the important high-frequency parameter of silicon material such as silicon conductivity. Finally, the SEM images of cross sections verify the current findings.