The ACE and I: how ACE inhibitors came to be

A method is provided for fabricating an array of memory cells for a dynamic random access memory. Each memory cell has an associated capacitor. An array of memory cell transistors is formed and each memory cell transistor has a source, a drain and a gate. The source is coupled to a bit line, and the gate is coupled to a word line. A lower conductive layer is formed over the array of memory cell transistors. The lower conductive layer is electrically coupled to the source of the memory cell transistors. A temporary insulation layer is formed over the lower conductive layer. A portion of the temporary insulation layer and the lower conductive layer are removed to form an electrically separate capacitor bottom plate for each memory cell and an inter-capacitor isolation region. A lateral portion of the temporary insulation layer is removed to form a capacitor sidewall spacing region. A protective layer is formed to fill the inter-capacitor isolation region and the capacitor sidewall spacing region. The temporary insulation layer is removed to expose a portion of the lower conductive layer. A portion of the exposed portion of the lower conductive layer is removed to form a U-shaped capacitor bottom plate. The protective layer is removed and a capacitor dielectric is formed. An upper conductive layer is formed to function as a top plate of the capacitor.