Enhanced Operation in Charge-Trapping Nonvolatile Memory Device With $\hbox{Si}_{3}\hbox{N}_{4}/\hbox{Al}_{2}\hbox{O}_{3}/\hbox{HfO}_{2}$ Charge-Trapping Layer

A stacked Si 3 N 4 /HfO 2 charge-trapping (CT) layer was proposed to improve erase operation and retention for CT nonvolatile memory (NVM) devices. The improvement can be attributed to the smaller valence band offset of Si 3 N 4 to Si and the higher barrier for electron detrapping from HfO 2 to Si 3 N 4 . The programming and retention characteristics of CT NVM devices can be further enhanced by inserting Al 2 O 3 between Si 3 N 4 and HfO 2 as the CT layer. This is because most of the injecting charges are trapped at the Si 3 N 4 /Al 2 O 3 interface, and Al 2 O 3 also provides a high barrier for electron detrapping.