On the Reliability of FeFET On-Chip Memory

FeFET is a promising technology for non-volatile on-chip memories. It is rapidly attracting an ever-increasing attention from industry. The advantage of FeFETs is full compatibility with the existing CMOS process beside their low power consumption. To enable ultra-dense memories, 1-FeFET AND arrays were proposed in which a memory cell is formed from a single FeFET. All access transistors, which are traditionally needed to operate memory cells, are removed. This imposes a new reliability challenge due to indirect write disturbances. In this work, we are the first to investigate the reliability of FeFET memories from device to system level. We develop a unified model capturing the impact of both indirect disturbances and direct writes on the reliability of FeFET cells. We then investigate different array sizes, write voltages, write methods under the effect of a wide range of workloads using CPU cache as an example of on-chip memory. We demonstrate that indirect write disturbances are the dominate effect degrading the reliability of FeFET memories. For most cells, it contributes over 90% to the overall induced degradation. This provides guidelines for researchers at both device and circuit levels to optimize the FeFET reliability further, while considering the hidden impact of workloads.