An investigation of reliability and variability issues in nanoscale SOI and multi-gate MOSFETs: modelling, simulation and characterization

This work encapsulates research being carried out in the Device and Wafer Level Characterization Lab at the Department of Electrical Engineering, IIT Delhi in the field of nano-electronics device characterization and modeling. Performance of different multi-gate device architectures, as well as their reliability and variability in different working conditions is investigated using measurement and simulations. The reliability of 180-nm fully and partially-depleted SOI MOSFETs has been extensively studied against heavy-ion irradiation for outer space applications. Exposure to heavy ion radiation can result in single event effects in semiconductor-based devices and circuits. Therefore, the transient response to heavy ion irradiation is presented for 6T-SRAM cell. Moreover, self-heating (SH) is an undesirable phenomenon in highly scaled sub-10 nm devices and it is also a major reliability concern. The heat accumulation in devices due to SH is explored and a comparison among nanowire FET, FinFET, and iFinFET is presented. Our results show that the device performance will be affected for space as well as analog and digital applications due to self-heating and heavy-ion irradiations. Process variability is also an obstacle at sub-10 nm device design and its proper consideration is important for analog as well as digital circuit designs. Therefore, we have extracted a SPICE based compact model for nanowire FETs from the measured data. We then run Monte-Carlo simulations to incorporate the effects of process variations on the performance of nanowire-MOSFETs.