Invited) Parastic Elements in Gate Stacks and Contacts of Planar and Fin Transistors

Reduction of dimensions or scaling has reduced cost and enhanced performance of integrated circuits. These reduced dimensions have increased the importance of parasitic elements associated with the gate structure and contact structure to rf circuit design and more recently to microprocessors, standard products, and application specific integrated circuits. The net lists and compact models must account for the physical structure to enable scalability, must be efficient to enable circuit design and must be verifiable through hardware measurement. The hardware measurements can serve as a diagnostic tool for enhancing process technology of planar and FINFET field effect transistors.