Reduction methods for adapting optical network on chip topologies to 3D architectures

Optical Network on Chip (ONoC) architectures are emerging as promising candidates to solve congestion and latency issues in future embedded systems. In this work, we examine how a scalable and fully connected ONoC topology can be reduced to fit specific connectivity requirements in heterogeneous 3D architectures. Through such techniques, it is possible to reduce the number of required wavelengths, laser sources, photodetectors and optical switches as well as the length of the longest optical path. This allows constraints to be relaxed on source wavelength accuracy and passive filter selectivity, and also alleviates power and area issues by reducing the number of active devices. The proposed reduction method was successfully applied to multiple heterogeneous 3D architectures.