Parity-preserving reversible flip-flops with low quantum cost in nanoscale

In recent years, reversible logic has attracted high importance because of its in-cognitive property of reduction in energy dissipation which is the main requirement in low-power digital circuits. Reversible logic is one of emerging fields of research, which is used in various fields such as low-power CMOS, DNA computing, quantum computing, fault tolerance and nanotechnology. A circuit is reversible if it has the same number of inputs and outputs, and there is a one-to-one correspondence between them. A reversible circuit is parity-preserving if the EXOR of the inputs is equal to the EXOR of the outputs. Flip-flops are considered as one of the most important digital designs that are widely used as building blocks in the design of sequential circuits. In this paper, two new 4 × 4 parity-preserving reversible blocks are first proposed, called PNM1 and PNM2, respectively. Quantum syntheses of the proposed blocks are carried out using the Miller et al. method. In the following, effective designs of parity-preserving reversible D, T and J-K flip-flops along with their master–slave versions are introduced using the proposed parity-preserving reversible blocks and DFG gates. Finally, a 4-bit asynchronous up-counter is designed using the proposed parity-preserving reversible D flip-flop and FRG gate. The results of the comparisons show that although the proposed structures are close to previous designs in terms of gate count, constant input and garbage output criteria, they are superior in terms of quantum cost.