An efficient tile size selection model based on machine learning

Abstract Tiling is a classic loop optimization to improve data locality and achieve coarse-grained parallelism. Tile size selection (TSS) plays an important role in tiling to determine the performance of tiled codes. Most of the previous TSS approaches involve much highly skilled manpower, but it is still difficult to find the optimal tile sizes. In this article, we propose an efficient TSS model using machine learning technique to predict optimal rectangular tile sizes for a given program on multi-core processors. A set of loop features is extracted on tiled codes to capture the locality of data references and the effect of vectorization in tiled loop dimensions. Using the features and corresponding best tile sizes, the generalized regression neural network is employed to build the TSS model, hiding the complicated interactions between tile sizes and underlying factors. Although the impact of multithreading is not directly considered in training the model, the predicted tile sizes can be well adapted to different numbers of threads. Experimental results show that the predicted tile sizes achieve 90% and 81% of the optimal performance on average for 20 selected benchmarks on an Intel Xeon and an IBM Power6 multi-core platforms, respectively. The optimal performance is delivered by the tile sizes that are obtained through a heuristically exhaustive search. Our TSS model outperforms an artificial neural network (ANN)-based TSS prediction model which depends on the prefetched features by over 9% in average performance for 9 benchmarks. It also outperforms a state-of-the-art analytical TSS model which uses the cache set associativity and interaction with the single instruction multiple data (SIMD) units to estimate the optimal tile sizes by over 7% in average performance for 7 benchmarks.