Patterning strategy and performance of 1.3NA tool for 32nm node lithography
2008
We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure
conditions. The simulation and experimental results indicate that the minimum pitches should be
determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated
feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um 2 area is clearly
resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability.
There is no immersion induced defects.
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