Ultra-low resistivity in-situ phosphorus doped Si and SiC epitaxy for source/drain formation in advanced 20 nm n-type field effect transistor devices

Abstract We present an effective epitaxy process based on a cyclical deposition-etch (CDE) technique to obtain ultra-low resistivity in situ phosphorus-doped silicon carbon (SiCP) layers for raised source/drain applications. The combined low process temperature and high growth rate of the CDE technique is shown to maximize the incorporation of phosphorus and carbon into the crystal. We also present a complementary procedure based upon high-temperature annealing to further improve the phosphorus activation. This process and procedure enable the formation of raised SiCP source/drains on advanced 20 nm fully-depleted-silicon-on-insulator devices with a carrier density up to 3 × 10 20  cm − 3 for 5 × 10 20  cm − 3 total P, and with fully-substitutional carbon in the range from 0% to 2%. It was found that a 1250 °C millisecond laser anneal improves resistivity by 30% and 42% for SiP and SiC 2.1% P, respectively. This result is in contrast with a 1060 °C spike anneal, where the gain in activated P is shown to be insignificant for SiCP. It is shown that the formation of C clusters or precipitates during spike anneal adversely affects P activation. With an optimized annealing process, resistivity values as low as 0.46 MΩ cm for SiC 2.1% P and 0.3 MΩ cm for SiP were obtained.