Resistance Switching Behaviors of RRAM Having W/CeO2/Si/TiN Structures

The resistance switching behaviors of RRAM having W/CeO2/Si/TiN structures is studied, which exhibits bipolar switching and ohmic contact in low resistance state. Furthermore, compared with W/CeO2/TiN deices, the RRAM incorporating Si layer exhibits a large ratio of resistance in high resistance state (HRS) with respect to that in low resistance state (LRS), and better repetition characteristics. Instruction Recently, RAM (RRAM) utilizing resistance switching has been extensively studied as a promising candidate for the next generation of nonvolatile memory. Although great progress has been achieved, the performance of scaled RRAM devices is still limited by their efficiency and reliability [1]. Cerium oxide is promising for its application to advanced RRAM because it can be used as solid electrolyte having high dielectric constant and high ion conductivity. [2]. In addition, cerium oxide is easy to react with Si to form silicate [3], which modifies structure and concentration of vacancies in cerium oxide film. Thus, the purpose of this study is to clarify the resistance switching behaviors of CeO2 based devices and improving their function by incorporating Si layer. Experiment The structure of the devices is schematically shown in Fig.1. Fabrication started from growing a SiO2 layer on highly doped Si wafers (below 0.02 Ω cm) by thermal oxidation, followed by formation of contact windows through SiO2 layer. A TiN layer and a Si layer, ranging from 0 nm to 2 nm, were then deposited by RF sputtering, and subsequently, a CeO2 layer, ranging from 10 nm to 15 nm, was deposited by e-beam evaporation. Then a W layer was in-situ deposited by sputtering and was patterned to form electrodes having area of 20 μm square. Finally, Al was evaporated as a back contact followed by RTA in N2 ambient for 30 s at 400 oC. Result and Discussion Figure 2 shows the bipolar resistance switching behaviors of W/CeO2 (20 nm) /Si (1 nm)/TiN device. The window, expressed by resistance in HRS/resistance in LRS, takes a value of about 15 and power consumption is lower than 3 mW. Besides, linear relationship between current and voltage at LRS indicates ohmic contact is formed. Furthermore, as shown in Fig. 3, by incorporating Si layer the device exhibits enlarged window and better repetition characteristics. After 60 times cycles, devices incorporating Si layer still has a window of about 17, while the window of the device without incorporating Si layer degraded to 1.7. Conclusion W/CeO2/Si/TiN still exhibits stable resistance switching with a window of about 15 when the thickness of CeO2 is scaled down to 20 nm. Power consumption per switching is below than 3 mW, and ohmic contact is obtained in LRS. In addition, Si layer incorporated in the device enlarge the windows and improve the repetitions characteristics remarkably. References [1] R. Waser, et al., Nature Materials 6, p.833(2007). [2] C. Lin, et al., Surface & Coating Technology 203, p.480-483, (2008). [3] K. Kakushima, et al., VLSI Tech. Dig. p.69-70(2010). Fig.1. Schematic illustration of the RRAM device having W/CeO2/Si/TiN structure. 0.0E+00 2.0E-04 4.0E-04 6.0E-04 8.0E-04 1.0E-03 1.2E-03 -3 -2 -1 0 1 2 3 Bias(V) ∣ C ur re en t ∣ (A )