A nanostructured micellar diblock copolymer layer affects the memory characteristics and packing of pentacene molecules in non-volatile organic field-effect transistor memory devices

Organic field-effect transistor (OFET) memory devices incorporating the copolymer polystyrene-block-poly(4-vinylpyridine) (PS56k-b-P4VP8k) layer, which features a thickness-dependent micellar nanostructure (P4VP-core, PS-shell), as a charge trapping layer can exhibit tunable memory windows for p-channel applications. For instance, the memory window increased substantially from 7.8 V for the device incorporating a 60 nm thick PS56k-b-P4VP8k layer to 21 V for the device incorporating a 27 nm thick layer, an increase of more than 2.5 times. Using simultaneous synchrotron grazing-incidence small-angle X-ray scattering and wide-angle X-ray scattering to probe the nanostructured micellar PS56k-b-P4VP8k layer and the pentacene layer positioned directly on the top of the copolymer layers, respectively, we were able to elucidate the structural characteristics of the bilayer and to correlate their effects with the memory performances of devices with similar architectures. For the PS56k-b-P4VP8k layers, we found that the inter-micelle distance and their lateral arrangements depended on the layer thickness: the thickness of the PS shells in the lateral direction decreased upon increasing the layer thickness, as did the memory window for the OFET device that incorporated the PS56k-b-P4VP8k layers, showing a strong dependence of the threshold voltage shifts (i.e., memory window) on the distance between the micelles. Additionally, for the molecular packing of the pentacene layer positioned on the copolymer layer, we found that the PS56k-b-P4VP8k layers affected not only the orientation of the pentacene molecules but also their grain sizes, thereby affecting the hole mobility of the memory devices. These results suggest that tuning the micellar nanostructure of the block copolymer thin film that was used as a trapping layer can be a simple and effective way for optimizing the memory window and affecting the hole mobility of OFET memory devices.