CHARACTERIZATION OF SLOW TRAP IN MOS CAPACITOR

Our study is devoted to an analysis of the defects in "slow states", which are supposed to be located in oxide close to the interface and which exchange carriers with the semiconductor by tunnel effect and in MOS capacities by using the Voltage Step technique. The aim is to clarify further resul ts about this technique which were published earlier [1, 2, 3]. The evaluation of Tunnel depths, which play a very important role in the capture from the variation of the energy and the gate bias voltage, was made starting from the simulation of the potential of surface φs(Vg) using equations TMOS [4,5]. The MOS capacitor, used in the experiment was Ntype (substarte P), with an oxide thickness of 130A 0