Status of the CEA Saclay R&D activities on pixelised readout of TPC

We report on the status of our last R&D activities on a pixelised readout for a TPC using the TimePix chip. We summarize the results of the wafer tests at CERN in which we participated inside the SiTPC collaboration. The yield of good chips reaches 73 %. Based on Micromegas detector technology we built a small chamber with a 6 cm height field cage using this pixel technology protected by a resistive layer. We present the first X-rays observed in this digital micro-TPC. The design and construction of a deliverable panel made up of a matrix of 2 x 4 TimePix chips are in progress with the aim of being tested in the LC-TPC Large Prototype some time next year within the EUDET facility. 1 david.attie@cea.fr