Impact of Thermal Effects on the Performance of the Power Gating Circuits Using NEMS, FinFETs, and NWFETs

In this article, the power gating (PG) technique is analyzed using nano-electro-mechanical switches (NEMS), FinFETs, and nanowire field-effect transistors (NWFETs). We have used detailed circuit level simulations using well-calibrated models to obtain the conditions for net energy saving with thermal effects. We demonstrate that for a benchmark 17-stage buffer chain circuit, the NEMS PG will be superior to sub-10-nm FinFETs and NWFETs-based gating when the $ {T}_{ \text{on}}/ {T}_{ \text{off}}$ ratio is less than 0.1 at room temperature. The ratio increases as temperature increases. Circuit simulations show that the energy gain ( $ {T}_{\text {on}}/ {T}_{ \text{off}} = {10}^{-{4}}$ ) due to NEMS gating increases by 3.6 times with reference to NWFETs and 7.3 times as compared to FinFETs-based gating when the temperature increases from 30 °C to 80 °C. NWFETs require a longer breakeven cycle for PG to become more energy-efficient than FinFETs due to its better gate control over the channel.