The VLSI Realization of Sign-Magnitude Decimal Multiplication Efficiency

Multiplication is a dynamic procedure in which intermediate partial products (IPPs) are typically picked from a set of multiples of pre-calculated radix-10 X. Many plays require just [0, 5] by encoding the Y digits to a one-hot representation of the signed digits in [−5, 5]. This eliminates the sense of choice at the cost of additional IPP. Two-complement signed-digit (TCSD) encoding is also used to characterize IPPs that allow dynamic negation (through one xor per bit of X multiples) of Y-coded digits in [−5, − 1]. With the generation of 17 IPPs for 16-digit operands, we are able to launch a partial product reduction (PPR) with 16 IPPs that improve VLSI regularity. We thus save 75% of the negating xors by encoding sign-magnitude signed-digit (SMSD). For first-level PPR, we create an efficient adder with two SMSD input numbers, the total number defined by the TCSD encoding. Multi-level TCSD 2:1 reduction results in two TCSD combined partial items jointly subject to a special early-initiated conversion scheme for the final binary-coded decimal portion. As such, the VLSI implementation of a 16-digit parallel decimal multiplier is synthesized where results show some increase in efficiency over previous similar designs.